# Glossary

This document collects the professional terms and abbreviations used in the Triton-distributed-ascend documentation, organized by category for easy reference.

## Compilation and IR

| Abbreviation | Full Name | Description |
| --- | --- | --- |
| IR | Intermediate Representation | Intermediate representation |
| AST | Abstract Syntax Tree | Abstract syntax tree |
| MLIR | Multi-Level Intermediate Representation | Multi-level intermediate representation, an extensible compiler infrastructure in the LLVM ecosystem; both Distributed Dialect and HIVM Dialect are built on top of it |
| TTIR | Triton IR | Intermediate representation at the Triton dialect level, also the name of a stage in the compilation pipeline |
| LLVM | (Proper name, no longer corresponds to an acronym expansion) | The target IR / backend infrastructure for the GPU path |
| HIVM | Ascend backend core IR dialect name | Used as a proper noun in `AscendNPU-IR`/`bishengir` code, no official acronym expansion found |
| DPS | Destination-Passing Style | An IR design pattern that passes computation results through pre-allocated init/output values |
| CSE | Common Subexpression Elimination | Common subexpression elimination |
| LICM | Loop-Invariant Code Motion | Loop-invariant code motion |
| `TT_*` (e.g., `TT_Type`/`TT_Ptr`/`TT_IntLike`) | Triton Type | Prefix for Triton dialect type constraints in TableGen |

## Hardware and Execution Units

| Abbreviation | Full Name | Description |
| --- | --- | --- |
| NPU | Neural Processing Unit | Neural processing unit, referring to Huawei Ascend AI processors in this document |
| GPU | Graphics Processing Unit | Graphics processing unit |
| GM | Global Memory | Global memory, device-side globally addressable memory |
| UB | Unified Buffer | Unified buffer, AICore on-chip temporary buffer |
| AIC | AI Cube Core | Matrix unit, responsible for matrix operations |
| AIV | AI Vector Core | Vector unit, responsible for vector computation and low-latency communication |
| PE | Processing Element | Processing element, corresponding to a rank / process / device participant |

## Communication Engines and Protocols

| Abbreviation | Full Name | Description |
| --- | --- | --- |
| SHMEM | Symmetric Hierarchical Memory / Shared Memory | Symmetric memory communication library, referring to `shmem`/`aclshmem` symmetric heap communication library in this document |
| ACLSHMEM | Combination of ACL (AscendCL) and SHMEM | Prefix naming for symmetric heap communication interfaces/symbols in this document |
| MTE | Memory Transfer Engine | Memory transfer engine, data movement engine on Ascend AICore side |
| SDMA | System Direct Memory Access | System direct memory access |
| UDMA | UB Direct Memory Access | Unified direct memory access |
| RDMA | Remote Direct Memory Access | Remote direct memory access |
| RoCE / ROCE | RDMA over Converged Ethernet | RDMA over converged Ethernet |
| TLS | Transport Layer Security | Transport layer security protocol |
| QP | Queue Pair | Queue pair |
| SQ | Send Queue | Send queue |
| SQE | Send Queue Element | Send queue element |
| WQE | Work Queue Element | Work queue element |
| SGE | Scatter/Gather Element | Scatter/gather element |

## Other

| Abbreviation | Full Name | Description |
| --- | --- | --- |
| SIMD | Single Instruction Multiple Data | Single instruction multiple data |
| SDK | Software Development Kit | Software development kit |